module MBR(
    input clk,
    input data_in_en,
    input data_out_en,
    input imm_out_en,//MBR#IMM_out [9:0]立即数
    input imm_out_en_7bit,//MBR#IMM_out [6:0]立即数
    inout [15:0] data_bus,
    input rst_n,
    input read_form_MEM_en,//MBR<=MEMORY控制信号
    input [15:0] data_form_MRMORY,//input from MRMORY
    output [15:0] data_2_MEM//output to MRMORY
    );
    reg [15:0] data_reg;
    always @(posedge clk ) begin
        if (rst_n == 1'b0) begin
            data_reg <= 16'h0000;
        end
        else if (data_in_en) begin
            data_reg <= data_bus;
        end else if (read_form_MEM_en) begin
            data_reg <= data_form_MRMORY; 
        end
    end
    assign data_bus = data_out_en ? data_reg : (imm_out_en ? { {6{data_reg[9]}},data_reg[9:0] } : (imm_out_en_7bit ? { {9{data_reg[6]}},data_reg[6:0] } : 16'hzzzz));
    assign data_2_MEM = data_reg;
endmodule